seiko epson corporation 1 pf736-04 E0C623E 4-bit single chip microcomputer n description the E0C623E is a cmos single-chip microcomputer composed of the 4-bit core cpu e0c6200a, rom, ram, lcd driver, time base counter, stopwatch timer, svd circuit and sound generator. the E0C623E provides an excellent solution for low-power consumption systems with clock functions. n features l cmos lsi 4-bit parallel processing l clock ..................................................... 32.768khz (typ.) / 1mhz (typ.) l instruction set ........................................ 100 instructions l instruction execution time ..................... during operation at 32.768khz : 153 m sec, 214 m sec, 366 m sec (depending on instruction) during operation at 1mhz : 5 m sec, 7 m sec, 12 m sec l rom capacity ....................................... 2,048 words 12 bits l ram capacity ........................................ 144 words 4 bits l input port ............................................... 4 bits (pull down resistors are available by mask option) l output port ............................................ 5 bits (general purpose output) 1 bit (sound output) 1 bit (sound reverse or general purpose output) 1 bit (clock or general purpose output) the clock frequency can be selected from osc3 or 256hz to 32khz by mask option. l i/o port .................................................. 4 bits l lcd driver ............................................. 42 segments 4 commons / 38 segments 8 commons (switching between 1/4 duty and 1/8 duty is available by mask option) l sound generator ................................... 8 programmable sounds l built-in stopwatch timer l built-in supply voltage detection (svd) circuit l interrupt ................................................. external : input interrupt 2 systems internal : timer interrupt 2 systems l current consumption ............................ E0C623E halt mode (32khz) : 1.5 m a (typ.) operating mode (32khz) : 4.0 m a (typ.) e0c62l3e halt mode (32khz) : 1.5 m a (typ.) operating mode (32khz) : 4.0 m a (typ.) e0c62a3e operating mode (1mhz) : 150 m a (typ.) l package ................................................ qfp5-80pin (plastic), qfp14-80pin (plastic) die form n line up l core cpu architecture l svd circuit l sound generator model supply voltage 1.5v (1.1v to 3.5v) 3.0v (2.2v to 5.5v) 3.0v (2.2v to 5.5v) e0c62l3e E0C623E e0c62a3e clock (oscillation) 32khz (crystal or cr) 32khz (crystal or cr) 32khz (crystal or cr) & 1mhz (ceramic or cr) wide voltage operation products
2 E0C623E n block diagram n pin configuration qfp5-80pin k00?03 test p00?03 r00?03 r10, r11 osc1 osc2 osc3 osc4 reset interrupt generator input port test port i/o port output port clock timer stopwatch timer ram 144 words x 4 bits lcd driver power controller sound generator core cpu e0c6200a system reset control rom 2,048 words x 12 bits osc seg0?eg37 com7/seg38 com6/seg39 com5/seg40 com4/seg41 com0?om3 v dd v l1 ? l4 ca?d v s1 v ss sout r12 (so) 41 64 25 40 index 24 1 80 65 E0C623E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38/com7 seg39/com6 seg40/com5 seg41/com4 com3 com2 com1 pin no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 com0 cd cc cb ca v l4 v l3 v l2 v l1 v ss osc4 osc3 v s1 osc2 osc1 v dd p00 p01 p02 p03 pin no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 r10 r11 r12 sout r00 r01 r02 r03 k00 k01 k02 k03 test reset seg0 seg1 seg2 seg3 seg4 seg5 pin no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 n.c. : no connection seg6 n.c. seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 pin no. pin name
3 E0C623E pin name v dd v ss v s1 v l1 ? l4 ca?d osc1 osc2 osc3 osc4 k00?03 p00?03 r00?03 r10 r11 r12 sout seg0?eg37 com0?om3 seg38?eg41 com4?om7 reset test pin no. qfp5 36 30 33 29?6 25?2 35 34 32 31 49?2 37?0 45?8 41 42 43 44 1?3 55?0 21?8 14?7 54 53 qfp14 34 28 31 27?4 23?0 33 32 30 29 48?1 35?8 44?7 39 41 42 43 54?0 1?1 19?6 12?5 53 52 (i) (i) i o i o i i/o o o o o o i i function power source (+) pin power source (? pin internal logic and oscillation system regulated voltage power source pin lcd system power source pins lcd system booster capacitor connection pins crystal or cr oscillation input pin crystal or cr oscillation output pin ceramic or cr oscillation input pin (e0c62a3e) ceramic or cr oscillation output pin (e0c62a3e) input port pins i/o port pins output port pins r10: fout output available through mask option selection r12: sound inverted output available through mask option selection sound signal output pin lcd segment output pins lcd common output pins lcd segment output pins (when 1/4 duty is selected) lcd common output pins (when 1/8 duty is selected) initial reset input pin test input pin i/o n pin description qfp14-80pin 41 60 21 40 index 20 1 80 61 E0C623E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38/com7 seg39/com6 seg40/com5 seg41/com4 com3 com2 com1 com0 cd pin no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 cc cb ca v l4 v l3 v l2 v l1 v ss osc4 osc3 v s1 osc2 osc1 v dd p00 p01 p02 p03 r10 n.c. pin no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 r11 r12 sout r00 r01 r02 r03 k00 k01 k02 k03 test reset seg0 seg1 seg2 seg3 seg4 seg5 seg6 pin no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 n.c. : no connection seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 pin no. pin name
4 E0C623E n electrical characteristics l absolute maximum ratings (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l4 are internal voltage , c 1 ? 8 =0.1 f) high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current low level output current common output current segment output current (lcd output) common output current segment output current (lcd output) v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i ol1 i oh2 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v v v v a a a a ma ma a a a a a a a a v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v ol1 =0.9? ss v oh2 =-0.05v v ol2 =v l3 +0.05v v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l4 +0.05v v oh5 =-0.05v v ol5 =v l4 +0.05v max. 0 0 0.8? ss 0.90? ss 0.5 16 100 0 -1.0 -3 -3 -3 -3 min. 0.2? ss 0.10? ss v ss v ss 0 5 30 -0.5 3.0 3 3 3 3 k00?03, p00?03 reset, test k00?03, p00?03 reset, test k00?03, p00?03 k00?03 p00?03, reset, test k00?03, p00?03, reset, test r00?03, r10?12 p00?03, sout r00?03, r10?12 p00?03, sout com0?om3 seg0?eg41 com0?om7 seg0?eg37 typ. characteristic symbol unit condition 1/4 duty 1/4 duty 1/8 duty 1/8 duty l dc characteristics E0C623E/62a3e l recommended operating conditions E0C623E e0c62l3e e0c62a3e rating symbol unit value supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time allowable dissipation * 2 * 1 * 2 v ss v i v iosc s i vss topr tstg tsol p d v v v ma ? ? mw -6.0 to 0.5 v ss - 0.3 to 0.5 v s1 - 0.3 to 0.5 10 -20 to 70 -65 to 150 260?, 10sec (lead section) 250 (v dd =0v) the permissible total output current is the sum total of the current that simultaneously flows from the output pins (or is draw n in). in case of plastic package (qfp5-80pin, lqfp14-80pin). condition symbol unit remark supply voltage oscillation frequency v ss f osc1 v khz v dd =0v (ta=-20 to 70?) max. -2.2 50 typ. -3.0 32.768 min. -5.5 20 condition symbol unit remark supply voltage oscillation frequency * 1 when switching to the heavy load protection mode. the svd circuit is turnd off. * 2 the voltage which can be displayed on the lcd panel will differ according to the characteristics of the lcd panel. v ss f osc1 v v khz v dd =0v v dd =0v, with software control (ta=-20 to 70?) max. -1.1 -0.9 * 2 50 typ. -1.5 -1.5 32.768 min. -3.5 -3.5 20 * 1 condition symbol unit remark supply voltage oscillation frequency v ss f osc1 f osc3 v khz khz v dd =0v duty 50?% (ta=-20 to 70?) max. -2.2 1,200 typ. -3.0 32.768 1,000 min. -5.5 300
5 E0C623E lcd drive voltage svd voltage svd circuit response time power current consumption (normal mode) power current consumption (heavy load protection mode) * 1 v l1 v l2 v l3 v l4 v svd t svd i op1 i op2 i op1 i op2 v v v v v s a a a a a a a a connect 1m w load resistor between v dd and v l1 (no panel load) connect 1m w load resistor between v dd and v l2 (no panel load) connect 1m w load resistor between v dd and v l3 (no panel load) connect 1m w load resistor between v dd and v l4 (no panel load) during halt during execution during halt during execution during halt during execution during halt during execution max. -0.95 2? l1 0.9 3? l1 0.9 4? l1 0.9 -1.10 100 3.0 7.0 10.5 14.0 6.0 12.0 20.5 27.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 4? l1 -0.1 -1.30 (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, c g =25pf, ta=25 c, v s1 /v l1 ? l4 are internal voltage , c 1 ? 8 =0.1 f) typ. -1.05 -1.20 1.5 4.0 6.0 8.7 2.5 7.0 11.5 16.5 no panel load osc1: crystal oscillation no panel load osc1: cr oscillation no panel load osc1: crystal oscillation no panel load osc1: cr oscillation the svd circuit is off status. * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 characteristic symbol unit condition (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l4 are internal voltage , c 1 ? 8 =0.1 f) high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current low level output current common output current segment output current (lcd output) common output current segment output current (lcd output) v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i ol1 i oh2 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v v v v a a a a a a a a a a a a a a v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1? ss v ol1 =0.9? ss v oh2 =-0.05v v ol2 =v l3 +0.05v v oh3 =-0.05v v ol3 =v l3 +0.05v v oh4 =-0.05v v ol4 =v l4 +0.05v v oh5 =-0.05v v ol5 =v l4 +0.05v k00?03, p00?03 reset, test k00?03, p00?03 reset, test k00?03, p00?03 k00?03 p00?03, reset, test k00?03, p00?03, reset, test r00?03, r10?12 p00?03, sout r00?03, r10?12 p00?03, sout com0?om3 seg0?eg41 com0?om7 seg0?eg37 typ. characteristic symbol unit condition 1/4 duty 1/4 duty 1/8 duty 1/8 duty max. 0 0 0.8? ss 0.90? ss 0.5 10 60 0 -200 -3 -3 -3 -3 min. 0.2? ss 0.10? ss v ss v ss 0 2.0 9.0 -0.5 700 3 3 3 3 e0c62l3e e0c62l3e lcd drive voltage svd voltage svd circuit response time power current consumption (normal mode) power current consumption (heavy load protection mode) * 1 v l1 v l2 v l3 v l4 v svd t svd i op1 i op2 i op1 i op2 v v v v v s a a a a a a a a connect 1m w load resistor between v dd and v l1 (no panel load) connect 1m w load resistor between v dd and v l2 (no panel load) connect 1m w load resistor between v dd and v l3 (no panel load) connect 1m w load resistor between v dd and v l4 (no panel load) during halt during execution during halt during execution during halt during execution during halt during execution max. 0.5? l2 +0.1 -1.95 3? l1 0.9 4? l1 0.9 -2.25 100 3.0 7.0 10.5 14.0 33.0 37.0 40.5 44.0 min. 0.5? l2 -0.1 -2.25 3? l1 -0.1 4? l1 -0.1 -2.55 (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v s1 /v l1 ? l4 are internal voltage , c 1 ? 8 =0.1 f) typ. -2.10 -2.40 1.5 4.0 6.0 8.7 11.5 14.0 16.0 18.7 no panel load osc1: crystal oscillation no panel load osc1: cr oscillation no panel load osc1: crystal oscillation no panel load osc1: cr oscillation the svd circuit is off status. * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 characteristic symbol unit condition l analog circuit characteristics and current consumption E0C623E
6 E0C623E e0c62a3e E0C623E/62a3e (osc1 cr oscillation circuit) e0c62l3e (osc1 crystal oscillation circuit) characteristic symbol unit condition oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance * 1 items enclosed in parentheses ( ) are those used when operating in the heavy load protection mode. vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak v v pf ppm ppm ppm v m w (v ss ) t sta 3sec (v ss ) t stp 10sec including the parasitic capacitance inside the ic v ss = -1.1 to -3.5v (-0.9v) * 1 c g = 5 to 25pf (v ss ) between osc1 terminal and v dd , v ss max. 5 10 -3.5 min. -1.1 -1.1(-0.9) * 1 -10 40 200 (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) typ. 20 l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. E0C623E/62a3e (osc1 crystal oscillation circuit) characteristic symbol unit condition oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak v v pf ppm ppm ppm v m w (v ss ) t sta 3sec (v ss ) t stp 10sec including the parasitic capacitance inside the ic v ss = -2.2 to -5.5v c g = 5 to 25pf (v ss ) between osc1 terminal and v dd , v ss max. 5 10 -5.5 min. -2.2 -2.2 -10 40 200 (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25?c) typ. 20 lcd drive voltage svd voltage svd circuit response time power current consumption (normal mode) power current consumption (heavy load protection mode) * 1 * 2 v l1 v l2 v l3 v l4 v svd t svd i op1 i op2 i op3 i op1 i op2 i op3 v v v v v s a a a a a a a a a a connect 1m w load resistor between v dd and v l1 (no panel load) connect 1m w load resistor between v dd and v l2 (no panel load) connect 1m w load resistor between v dd and v l3 (no panel load) connect 1m w load resistor between v dd and v l4 (no panel load) during halt during execution (32khz) during halt during execution (32khz) during execution (1mhz) during halt during execution (32khz) during halt during execution (32khz) during execution (1mhz) max. 0.5v l2 +0.1 -1.95 3v l1 0.9 4v l1 0.9 -2.25 100 3.0 7.0 60 60 360 33.0 37.0 90 90 420 min. 0.5v l2 -0.1 -2.25 3v l1 -0.1 4v l1 -0.1 -2.55 (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v s1 /v l1 ev l4 are internal voltage , c 1 ec 8 =0.1 f) typ. -2.10 -2.40 1.70 4.0 30 30 180 11.7 14.0 40 40 300 no panel load osc1: crystal oscillation no panel load osc1: cr oscillation no panel load osc3: cr or ceramic oscillation no panel load osc1: crystal oscillation no panel load osc1: cr oscillation no panel load osc3: cr or ceramic oscillation the osc3 oscillation circuit and svd circuit are off status. the svd circuit is off status. * 1 * 1 * 1 * 1 * 2 * 1 * 1 * 1 * 1 * 2 characteristic symbol unit condition oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage f osc1 vsta t sta vstp % v ms v v ss =-2.2 to -5.5v max. 30 min. -30 -2.2 -2.2 (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =850k w , ta=25?c) typ. 32.768khz 3 characteristic symbol unit condition
7 E0C623E e0c62l3e (osc1 cr oscillation circuit) unit: mm e0c62a3e (osc3 ceramic oscillation circuit) n package dimensions e0c62a3e (osc3 cr oscillation circuit) 20 0.1 25.6 0.4 41 64 14 0.1 19.6 0.4 25 40 index 0.35 0.1 24 1 80 65 2.7 0.1 0.26 3.4 max 2.8 1.5 0 12 0.15 0.05 0.8 12 0.1 14 0.4 41 60 12 0.1 14 0.4 21 40 index 0.18 20 1 80 61 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 0.5 +0.1 ?.05 +0.05 ?.025 plastic qfp5-80pin plastic qfp14-80pin oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage f osc1 vsta t sta vstp % v ms v v ss =-0.9 to -3.5v max. 30 min. -30 -0.9 -0.9 (unless otherwise specified: v dd =0v, v ss =-1.5v, r cr =850k w , ta=25?) typ. 32.768khz 3 characteristic symbol unit condition oscillation start voltage oscillation start time oscillation stop voltage vsta t sta vstp v ms v max. 5 min. -2.2 -2.2 (unless otherwise specified: v dd =0v, v ss =-3.0v, ceramic oscillator: 1mhz, c gc =c dc =100pf, ta=25?) typ. characteristic symbol unit condition v ss =-2.2 to -5.5v oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage f osc3 vsta t sta vstp % v ms v v ss =-2.2 to -5.5v max. 30 3 min. -30 -2.2 -2.2 (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =35k w , ta=25?) typ. 1mhz characteristic symbol unit condition
E0C623E notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 n basic external connection diagram piezo buzzer single terminal driving (piezo buzzer driving through pnp transistor) * 1 osc3 oscillation circuit can be used only for e0c62a3e. for the E0C623E and 62l3e, do not connect anything to terminals osc3 and osc4. * 2 in case 1/4 duty was selected with the mask op- tion, set cd and v l4 to n.c. (not connected). the c3 and c7 capacitor are not required. * 3 the potential of the substrate is v dd . ca cb cc cd v l1 v l2 v l3 v l4 v dd osc1 osc2 osc3 osc4 v s1 reset test v ss c 1 c 2 c 3 c 4 c 5 c 6 c 7 c gx x'tal 1.5v or 3.0v piezo buzzer r12 sout k00 k03 p00 p03 r00 r03 r10 r11 i i/o o seg0 com7/seg38 com6/seg39 com5/seg40 com4/seg41 com3 com0 lcd panel E0C623E e0c62l3e e0c62a3e o coil cp ceramic c gc c dc c 8 * 1 * 2 * 2 r cr1 r cr3 * 3 x'tal r ceramic r c , c c c1?8 cp crystal oscillator cr oscillation resistor ceramic oscillator cr oscillation resistor capacitor trimmer capacitor capacitor capacitor 32.768khz, ci(max.)=35k w 850k w 1mhz (typ.) 35k w 100pf 5?5pf 0.1 f 3.3 f cr1 cr3 gc gx dc
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